Motorola Placement Paper
T here are Three streams
1 hardware ( sps)
2 software (gsg)
ppt for 2 hours
hardware 13 questions 1hour and 15 minutes
software 20 questions
Draw the state transition diagram for sequence detector for the sequence 011. if the first bit detected is zero then SCRH should be asserted when the second bit is 1 the SCRH should remain asserted when the third bit is 1 the FOUND should be asserted and the SCRH should be disasserted. No bits should be left.
ts=0.5 and Th=0.7 (for the this is the setup time reqd and hold time reqd)
buffer has the delay of 1nsec
what is the setup time _________ns
what is the hold time ___________ns
for Each gate delay time is 0.5 ns
a. For each gate the delay time is 0.5 ns when will the glitch occur draw the glitch waveform.
b. How the circuit should be modified to avoid glitch.
describe the driving inverter? What inverter is weak and which has more strength? why?
what is the output of the following circuit?
Draw the output waveform for the following ckt Vtp=Vtn=1V
obtain expression for the output (the i/ps may not be in correct order)
Determine the output waveform input is
a. What is the output waveform
b. What will happen when the AND gate is replaced by OR gate
using 2:1 Mux and one inverter make XOR gate
using 2:1 Mux make a transparent latch (D f/f)
Design a ckt such that f (clk_out)=2 f (CLK_in) that is frequency doubling circuit is needed
Find the outputs of the following ckts
a). assume Vt = threshold voltage
Totally 20 questions were asked
* Most of them from C and datastructures (in equal nos)
* few from c++
Numbers sequential search has to compare ______ elements on worst and _______numbers on an average
Which of the following algorithm is not applicable for lived list representation of numbers